1. Field of the Invention
The present invention relates to a programmable logic circuit, and in particular to an antifuse-based programmable logic circuit with a wide AND functionality.
2. Description of the Related Art
Programmable logic arrays are well known in the art. A programmable logic array (PLA) is a combinational, two-level AND-OR device that is programmed to realize predetermined sum-of-products logic expressions. Some PLAs, instead of using AND gates and OR gates, are built using bipolar, TTL technology. FIG. 1 illustrates PLA 100 which includes three input lines 101, 102, and 103 and three output lines 107, 108, and 109. Buffers 105 provide the signals on input lines 101, 102, and 103 and their complements to lines 110. Another set of lines, 109, are formed orthogonally to lines 110. A voltage source Vcc is provided through resistors 104 to each vertical line 109.
At each crossing 111A of line 110 and 109, a diode 112 is placed in series with a fuse 113 (see blow-up 114). Specifically, fuse 113 is coupled to one of lines 109 and diode 112 is coupled to one of lines 110. Diodes in this configuration perform the equivalent logical function as AND gates (explained in detail in reference to FIG. 4).
Inverters 106 invert the signals on lines 109 and provide those inverted signals to supply lines 118, thereby actually performing a NAND function. As shown in FIG. 1, lines 118 are formed orthogonally to lines 115. The voltage source Vcc is also provided to lines 115 through resistors 116. Once again, at each crossing 111B of one of lines 118 and one of lines 115, a fuse 113 is placed in series with a diode 112, wherein fuse 113 is coupled to one of lines 118 and diode 112 is coupled to one of lines 115. Inverters 117 invert the signals on lines 115, thereby providing a NAND-NAND function at output leads 107, 108, and 109. Note that a NAND-NAND function is equivalent to performing an AND-OR function.
However, the use of fuses in the above configuration results in several disadvantages. In order to program the desired pattern into the fuses, selected fuses are blown by applying a high current through those fuses until the resulting heat and large current destroy the conduction path. Each fuse requires a relatively large area in order to dissipate the heat generated during programming without damaging nearby circuitry. Additionally, large transistors are required in the programing circuitry to deliver the required programming current. Accordingly, a fusible link array is undesirably large, and the area does not scale with increasingly fine geometries used in the state-of-the-art fabrication processes.
Therefore, a need arises for a programmable logic circuit which provides the logic capability of a fusible link array while minimizing silicon area.